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vishay siliconix SI7220DN document number: 73117 s-83052-rev. c, 29-dec-08 www.vishay.com 1 dual n-channel 60-v (d-s) mosfet features ? halogen-free accordin g to iec 61249-2-21 available ? trenchfet ? power mosfet ? new low thermal resistance powerpak ? package, 1 / 3 the space of an so-8 while thermally comparable applications ? synchronous rectification ? primary side switch product summary v ds (v) r ds(on) ( )i d (a) q g (typ.) 60 0.060 at v gs = 10 v 4.8 13 0.075 at v gs = 4.5 v 4.3 powerpak 1212-8 bottom view 1 2 3 4 5 6 7 8 s1 g1 s2 g2 d1 d1 d2 d2 3.30 mm 3.30 mm ordering information: SI7220DN-t1-e3 (lead (pb)-free) SI7220DN-t1-ge3 (lead (pb)-free and halogen-free) n-channel mosfet g 1 d 1 s 1 n-channel mosfet g 2 d 2 s 2 notes: a. surface mounted on 1" x 1" fr4 board. b. see solder profile ( www.vishay.com/ppg?73257 ). the powerpak 1212-8 is a leadless package. the end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. a solder fillet at the exposed copper tip cannot b e guaranteed and is not required to ensure adequate bottom side solder interconnection. c. rework conditions: manual soldering with a solder ing iron is not recommended for leadless components. absolute maximum ratings t a = 25 c, unless otherwise noted parameter symbol 10 s steady state unit drain-source voltage v ds 60 v gate-source voltage v gs 20 continuous drain current (t j = 150 c) a t a = 25 c i d 4.8 3.4 a t a = 70 c 3.8 2.7 pulsed drain current i dm 20 avalanche current l = 0 1 mh i as 11 single avalanche energy e as 6.1 mj continuous source current (diode conduction) a i s 2.2 1.1 a maximum power dissipation a t a = 25 c p d 2.6 1.3 w t a = 70 c 1.4 0.69 operating junction and storage temperature range t j , t stg - 55 to 150 c soldering recommendations (peak temperature) b, c 260 thermal resistance ratings parameter symbol typical maximum unit maximum junction-to-ambient a t 10 s r thja 38 48 c/w steady state 77 94 maximum junction-to-case (drain) steady state r thjc 4.3 5.4
www.vishay.com 2 document number: 73117 s-83052-rev. c, 29-dec-08 vishay siliconix SI7220DN notes: a. pulse test; pulse width 300 s, duty cycle 2 %. b. guaranteed by design, not s ubject to production testing. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. typical characteristics 25 c, unless otherwise noted specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. max. unit static gate threshold voltage v gs(th) v ds = v gs , i d = 250 a 13v gate-body leakage i gss v ds = 0 v, v gs = 20 v 100 na zero gate voltage drain current i dss v ds = 60 v, v gs = 0 v 1 a v ds = 60 v, v gs = 0 v, t j = 85 c 5 on-state drain current a i d(on) v ds 5 v, v gs = 10 v 20 a drain-source on-state resistance a r ds(on) v gs = 10 v, i d = 4.8 a 0.048 0.060 v gs = 4.5 v, i d = 4.3 a 0.061 0.075 forward transconductance a g fs v ds = 10 v, i d = 4.8 a 15 s diode forward voltage a v sd i s = 2.2 a, v gs = 0 v 0.8 1.2 v dynamic b total gate charge q g v ds = 30 v, v gs = 10 v, i d = 4.8 a 13 20 nc gate-source charge q gs 2.3 gate-drain charge q gd 2.6 gate resistance r g f = 1 mhz 2 tu r n - o n d e l ay t i m e t d(on) v dd = 30 v, r l = 30 i d ? 1 a, v gen = 10 v, r g = 6 10 15 ns rise time t r 10 15 turn-off delay time t d(off) 20 30 fall time t f 10 15 source-drain reverse recovery time t rr i f = 2.2 a, di/dt = 100 a/s 30 60 output characteristics 0 4 8 12 16 20 012345 v gs = 10 thru 5 v v ds - drain-to-source voltage (v) - drain current (a) i d 4 v 3 v transfer characteristics 0 4 8 12 16 20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 t c = 125 c - 55 c 25 c v gs - gate-to-source voltage (v) - drain current (a) i d
document number: 73117 s-83052-rev. c, 29-dec-08 www.vishay.com 3 vishay siliconix SI7220DN typical characteristics 25 c, unless otherwise noted on-resistance vs. drain current gate charge source-drain diode forward voltage - on-resistance ( ) r ds(on) 0.00 0.02 0.04 0.06 0.08 0.10 0 4 8 12 16 20 i d - drain current (a) v gs = 10 v v gs = 4.5 v 0 2 4 6 8 10 03691215 v ds = 30 v i d = 4.8 a - gate-to-source voltage (v) q g - total gate charge (nc) v gs 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 t j = 150 c t j = 25 c 20 1 v sd - source-to-drain voltage (v) - source current (a) i s 10 capacitance on-resistance vs. junction temperature on-resistance vs. gate-to-source voltage 0 200 400 600 800 1000 0 102030405060 v ds - drain-to-source voltage (v) c oss c iss c - capacitance (pf) c rss 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 - 50 - 25 0 25 50 75 100 125 150 v gs = 10 v i d = 4.8 a t j - junction temperature (c) r ds(on) - on-resistance (normalized) 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0246810 i d = 4.8 a - on-resistance ( ) r ds(on) v gs - gate-to-source voltage (v)
www.vishay.com 4 document number: 73117 s-83052-rev. c, 29-dec-08 vishay siliconix SI7220DN typical characteristics 25 c, unless otherwise noted threshold voltage - 1.0 - 0.8 - 0.6 - 0.4 - 0.2 0.0 0.2 0.4 0.6 - 50 - 25 0 25 50 75 100 125 150 i d = 250 a variance (v) v gs(th) t j - temperature (c) single pulse power 0 30 50 10 20 power (w) time (s) 40 100 600 0.1 0.001 1 10 0.01 safe operating area, junction-to-ambient 100 1 0.1 1 10 100 0.01 10 t a = 25 c single pulse - drain current (a) i d 0.1 i dm limited i d(on) limited r ds(on) limited by bv dss limited p(t) = 10 p(t) = 1 p(t) = 0.1 dc p(t) = 0.01 p(t) = 0.001 p(t) = 0.0001 v ds - drain-to-source voltage (v) * v gs > minimum v gs at which r ds(on) is specified * normalized thermal transient impedance, junction-to-ambient 10 -3 10 -2 1 10 600 10 -1 10 -4 100 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single pulse duty cycle = 0.5 square wave pulse duration (s) normalized eff ective transient thermal impedance 1. duty cycle, d = 2. per unit base = r thja = 77 c/w 3. t jm - t a = p dm z thja (t) t 1 t 2 t 1 t 2 notes: 4. surface mounted p dm
document number: 73117 s-83052-rev. c, 29-dec-08 www.vishay.com 5 vishay siliconix SI7220DN typical characteristics 25 c, unless otherwise noted notes: the minimum creepage between d1 and d2 for this 100 v device is 0.2 mm. please see powerpak 1212-8 outline drawing, document # 71656, for more information. vishay siliconix maintains worldwide manufacturing capability. pr oducts may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?73117 . normalized thermal transient impedance, junction-to-case 1 0.2 0.1 10 -3 10 -2 10 -1 10 -4 2 1 0.1 0.01 0.05 single pulse duty cycle = 0.5 square wave pulse duration (s) normalized effective transient thermal impedance 0.02
package information www.vishay.com vishay siliconix revison: 26-jan-15 1 document number: 71656 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 powerpak ? 1212, (single/dual) dim. millimeters inches min. max. min. max. a 0.79 1.12 0.031 0.044 a1 0 0.05 0 0.002 b 0.23 0.41 0.009 0.016 c 0.13 0.33 0.005 0.013 d 3.00 3.61 0.118 0.142 d1 2.95 3.21 0.116 0.126 d2 1.98 2.70 0.078 0.106 d4 0.31 typ. 0.012 typ. e 3.00 3.61 0.118 0.142 e1 2.95 3.21 0.116 0.126 e2 1.47 2.21 0.058 0.087 e3 1.75 1.98 0.069 0.078 e4 0.535 typ. 0.021 typ. e 0.65 bsc 0.026 bsc k 0.61 0.024 k1 0.35 0.014 h 0.15 0.51 0.006 0.020 l 0.15 0.56 0.006 0.022 l1 0.051 0.204 0.002 0.008 0 12 0 12 w 0.15 0.36 0.006 0.014 m 0.125 typ. 0.005 typ. ecn: c15-0077-rev. k, 26-jan-15 dwg: 5882 3. dimensions exclusive of mold flash and cutting burrs 1. notes: 2 inch will govern dimensions exclusive of mold gate burrs backside view of single pad backside view of dual pad detail z d1 d2 d1 e1 c a 45 1 8 d2 4 3 h 2 1 e b e2 l b d3(2x) 4 3 2 1 a1 z k k1 w m d4 e3 e4 d5 hk e4 e2 l d2 d4 e3 d5 l1 2 2 d e h
vishay siliconix an822 document number 71681 03-mar-06 www.vishay.com 1 powerpak ? 1212 mounting and thermal considerations johnson zhao mosfets for switching applic ations are now available with die on resistances around 1 m and with the capability to handle 85 a. while these die capabilities represent a major advance over what was available just a few years ago, it is important for power mosfet packaging technology to keep pace. it should be obvi- ous that degradation of a high performance die by the package is undesirable. powerpak is a new package technology that addresses these issues. the powerpak 1212-8 provides ultra-low thermal impedance in a small package that is ideal for space-constrained applications. in this application note, the powerpak 1212-8?s construction is described. fo llowing this, mounting information is presented. finally, thermal and electrical performance is discussed. the powerpak package the powerpak 1212-8 package (figure 1) is a deriva- tive of powerpak so-8. it utilizes the same packaging technology, maximizing the die area. the bottom of the die attach pad is exposed to provide a direct, low resis- tance thermal path to the substrate the device is mounted on. the powerpak 1212-8 thus translates the benefits of the powe rpak so-8 into a smaller package, with the same level of thermal performance. (please refer to application note ?powerpak so-8 mounting and thermal considerations.?) the powerpak 1212-8 has a footprint area compara- ble to tsop-6. it is over 40 % smaller than standard tssop-8. its die capacity is more than twice the size of the standard tsop-6?s. it has thermal performance an order of magnitude better than the so-8, and 20 times better than tssop-8. its thermal performance is better than all current smt packages in the market. it will take the advant age of any pc board heat sink capability. bringing the junc tion temperature down also increases the die efficiency by around 20 % compared with tssop-8. for applications where bigger pack- ages are typically required solely for thermal consider- ation, the powerpak 1212- 8 is a good option. both the single and dual po werpak 1212-8 utilize the same pin-outs as the single and dual powerpak so-8. the low 1.05 mm powerpak height profile makes both versions an excellent choice for applications with space constraints. powerpak 1212 single mounting to take the advantage of th e single powerpak 1212-8?s thermal performance see application note 826, recommended minimum pad patterns with outline drawing access for vishay siliconix mosfets. click on the powerpak 1212-8 single in the index of this document. in this figure, the drain land pattern is given to make full contact to the drain pa d on the powerpak package. this land pattern can be extended to the left, right, and top of the drawn pattern. this ex tension will serve to increase the heat dissipation by decreasing the ther- mal resistance from the foot of the powerpak to the pc board and therefore to the ambient. note that increasing the drain land area beyond a certain point will yield little decrease in foot-to-board and foot-to- ambient thermal resistance. under specific conditions of board configuration, copper weight, and layer stack, experiments have found that adding copper beyond an area of about 0.3 to 0.5 in 2 of will yield little improve- ment in thermal performance. figure 1. powerpak 1212 devices
www.vishay.com 2 document number 71681 03-mar-06 vishay siliconix an822 powerpak 1212 dual to take the advantage of the dual powe rpak 1212-8?s thermal performance, the minimum recommended land pattern can be found in application note 826, recommended minimum pad patterns with outline drawing access for vishay siliconix mosfets . click on the powerpak 1212-8 dual in the index of this doc- ument. the gap between the two drain pads is 10 mils. this matches the spacing of the two drain pads on the pow- erpak 1212-8 dual package. this land pattern can be extended to the left, right, and top of the drawn pattern. this extension will serve to increase the heat dissipation by decreasing the ther- mal resistance from the foot of the powerpak to the pc board and therefore to the ambient. note that increasing the drain land area beyond a certain point will yield little decrease in foot-to-board and foot-to- ambient thermal resistance. under specific conditions of board configuration, copper weight, and layer stack, experiments have found that adding copper beyond an area of about 0.3 to 0.5 in 2 of will yield little improve- ment in thermal performance. reflow soldering vishay siliconix surface- mount packages meet solder reflow reliability requirement s. devices are subjected to solder reflow as a preconditioning test and are then reliability-tested using tem perature cycle, bias humid- ity, hast, or pressure pot. the solder reflow tempera- ture profile used, and the temperatures and time duration, are shown in figures 2 and 3. for the lead (pb)-free solder profile, see http://www.vishay.com/ doc?73257. ramp-up rate + 6 c /second maximum temperature at 155 15 c 120 seconds maximum temperature above 180 c 70 - 180 seconds maximum temperature 240 + 5/- 0 c time at maximum temperature 20 - 40 seconds ramp-down rate + 6 c/second maximum figure 2. solder reflow temperature profile figure 3. solder reflow temperatures and time durations 210 - 220 c 3 c/s (max) 4 c/s (max) 10 s (max) 1 8 3 c 50 s (max) reflo w zone 60 s (min) pre-heating zone 3 c/s (max) 140 - 170 c maxim u m peak temperat u re at 240 c is allo w ed.
vishay siliconix an822 document number 71681 03-mar-06 www.vishay.com 3 thermal performance introduction a basic measure of a device?s thermal performance is the junction-to-case thermal resistance, r jc, or the junction to- foot thermal resistance, r jf. this parameter is measured for the device mounted to an infinite heat sink and is therefore a char acterization of the device only, in other words, independent of the properties of the object to which the device is mounted. table 1 shows a comparison of the power pak 1212-8, powerpak so-8, standard tssop-8 and so-8 equivalent steady state performance. by minimizing the junction-to- foot thermal resistance, the mosfet die temperature is very close to the tempera- ture of the pc board. consider four devices mounted on a pc board with a board temperature of 45 c (figure 4) . suppose each device is dissipating 2 w. using the junc- tion-to-foot thermal resistance characteristics of the powerpak 1212-8 and the other smt packages, die temperatures are determined to be 49.8 c for the pow- erpak 1212-8, 85 c for the standard so-8, 149 c for standard tssop-8, and 125 c for tsop-6. this is a 4.8 c rise above the board temperature for the power- pak 1212-8, and over 40 c for other smt packages. a 4.8 c rise has minimal effect on r ds(on) whereas a rise of over 40 c will cause an increase in r ds(on) as high as 20 %. spreading copper designers add additional copper, spreading copper, to the drain pad to aid in conducting heat from a device. it is helpful to have some in formation about the thermal performance for a given area of spreading copper. figure 5 and figure 6 show the thermal resistance of a powerpak 1212-8 single and dual devices mounted on a 2-in. x 2-in., four-layer fr-4 pc boards. the two inter- nal layers and the backside la yer are solid copper. the internal layers were chosen as solid copper to model the large power and ground planes common in many appli- cations. the top layer was cut back to a smaller area and at each step junction-to-ambient thermal resistance measurements were taken. the results indicate that an area above 0.2 to 0.3 square inches of spreading copper gives no additional thermal performance improvement. a subsequent experiment was run where the copper on the back-side was reduced, first to 50 % in stripes to mimic circuit traces, and then totally removed. no signif- icant effect was observed. table 1: eqivalent steady state performance package so-8 tssop-8 tsop-8 ppak 1212 ppak so-8 configuration single dual single dual single dual single dual single dual thermal resiatance r thjc (c/w) 20 40 52 83 40 90 2.4 5.5 1.8 5.5 figure 4. temperature of devices on a pc board 2.4 c/ w 49. 8 c po w erpak 1212 20 c/ w 8 5 c standard so- 8 pc board at 45 c 52 c/ w 149 c standard tssop- 8 40 c/ w 125 c tsop-6
www.vishay.com 4 document number 71681 03-mar-06 vishay siliconix an822 conclusions as a derivative of the powerpak so-8, the powerpak 1212-8 uses the same packaging technology and has been shown to have the same level of thermal perfor- mance while having a footprint that is more than 40 % smaller than the standard tssop-8. recommended powerpak 1212 -8 land patterns are provided to aid in pc board layout for designs using this new package. the powerpak 1212-8 combines small size with attrac- tive thermal characteristics. by minimizing the thermal rise above the boa rd temperature, powerpak simplifies thermal design considerations, allows the device to run cooler, keeps r ds(on) low, and permits the device to handle more current than a same- or larger-size mos- fet die in the standard tssop-8 or so-8 packages. figure 5. spreading copper - si7401dn 45 55 65 75 8 5 95 105 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 r a j h t (c/ w ) spreading copper (s q . in.) 100 % 50 % 0 % figure 6. spreading copper - junction-to-ambient performance r a j (c/ w ) h t 50 60 70 8 0 90 100 110 120 130 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 spreading copper (s q . in.) 100 % 0 % 50 %
application note 826 vishay siliconix www.vishay.com document number: 72598 1 revision: 14-apr-08 application note recommended minimum pads for powerpak ? 1212-8 dual 0.088 (2.235) recommended mi nimum pads dimensions in inches/(mm) 0.152 (3.860) 0.094 (2.390) 0.039 (0.990) 0.068 (1.725) 0.010 (0.255) 0.016 (0.405) 0.026 (0.660) 0.025 (0.635) 0.030 (0.760) return to index return to index 0.152 (3. 8 60) 0.039 (0.990) 0.016 (0.405) 0.026 (0.660) 0.025 (0.635) 0.030 (0.760) 0.039 (0.990) 0.039 (0.990) 0.06 8 (1.725) 0.010 (0.225) 0.094 (2.390) recommended minim u m pads for po w erpak 1212- 8 d u al dimensions in inches/(mm)
legal disclaimer notice www.vishay.com vishay revision: 02-oct-12 1 document number: 91000 disclaimer all product, product specifications and data are subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employee s, and all persons acting on it s or their behalf (collectivel y, vishay), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, repres entation or guarantee regarding the suitabilit y of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicable law, vi shay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation specia l, consequential or incidental damages, and (iii) any and all i mplied warranties, including warra nties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of products for certain type s of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in generic applications. such statements are not binding statements about the suitability of products for a particular application. it is the customers responsib ility to validate that a particu lar product with the properties descri bed in the product specification is suitable fo r use in a particular application. parameters provided in datasheets and/or specification s may vary in different applications an d performance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vish ays terms and condit ions of purchase, including but not limited to the warranty expressed therein. except as expressly indicate d in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vi shay product could result in personal injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk. pleas e contact authorized vishay personnel to ob tain written terms and conditions regarding products designed for such applications. no license, express or implied, by estoppel or otherwise, to any intellectual prope rty rights is granted by this document or by any conduct of vishay. product names and markings noted herein may be trad emarks of their respective owners. material category policy vishay intertechnology, inc. hereby certi fies that all its products that are id entified as rohs-compliant fulfill the definitions and restrictions defined under directive 2011/65/eu of the euro pean parliament and of the council of june 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (eee) - recast, unless otherwis e specified as non-compliant. please note that some vishay documentation may still make reference to rohs directive 2002/95/ ec. we confirm that all the products identified as being compliant to directive 2002 /95/ec conform to directive 2011/65/eu. vishay intertechnology, inc. hereby certifi es that all its products that are identified as ha logen-free follow halogen-free requirements as per jedec js709a stan dards. please note that some vishay documentation may still make reference to the iec 61249-2-21 definition. we co nfirm that all the products identified as being compliant to iec 61249-2-21 conform to jedec js709a standards.

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